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Design of 4 bits Combinational Lock Using VHDL

Author: Jenny Ebitonere Ogeh

This paper presents the design of a 4-bit programmable combinational lock. The first phase of this paper involves modelling the circuit using Finite State Machine (FSM) design. This include synchronization of the push buttons, design and implementation of a single clock pulse for each buttons using VHDL and the FSM design of the entire system. The system is connected to an alarm which turns ON whenever a wrong combination is entered, and each stage of the FSM is displayed on a seven segment display. The second phase involves the implementation of the FSM on FPGA using VHDL. Results are evaluated through some simulations and experimental tests using the FPGA board.

Key words:
Decoder, Finite State Machine (FSM), Level-to-pulse converter, synchronizer, seven segment display.

Volume 19, Issue 2, April 2014, pp. 898-904                    Download PDF

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