A 3-V 14-bit 75-MS/s CMOS pipeline analog-to-digital converter with 93.72-dB spurious-free dynamic range

Author: Ting Li, Chao You

Abstract:
This paper proposes a 14-bit 75-MS/s CMOS pipelined analog-to-digital converter (ADC). It also presents a novel configuration of the front-end stage with sample-and-hold function for a sample-and-hold amplifier (SHA)-less architecture. In order to improve accuracy, this research uses a combination of techniques, such as communicated feedback capacitor switching (CFCS), amplifiers with gain boosting, low noise dynamic comparators, and domain-extended digital error corrections. The ADC is fabricated in AMIS 0.5 µm CMOS. The ADC, with an active area of 4.5 mm2, consumes 264 mW, when a 32 MHz input is at 75-MS/s sample rate.

Keywords:
ADC, Communicated feedback capacitor switching, Domain-extended digital error correction, converter, Pipeline ADC 

Volume 19, Issue 1, March 2014, pp. 870-878                    Download PDF



References:


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